A Noble Design Methodology to Minimize Plasma Induced Damage Using a Distributed Network Model in VNAND Flash Memory

As the number of word-line layers increases in 3D NAND to improve bit density, the design of By-pass Via (BVia) becomes more difficult due to the increased amount of plasma- induced charge. Plasma analysis is difficult because it is a complex system involving the plasma source in the equipment chamber, loading and topology according to the real structure in the wafer, and the plasma discharge path. In this study, we conducted a series of calculations to interpret the BVia burnout failure quantitatively. The tungsten melting phenomenon was explained in connection with plasma simulation, molecular dynamics, electromagnetic simulation, and heat transfer models. We also proposed a novel methodology to optimize BVia arrangement using a distributed resistor network, which can overcome computing power constraints for product-level design. By introducing a new design methodology, we obtained a damage-free BVia arrangement at the product level.