FPGA-Based Implementation of Polar Code Using Successive Cancelation Decoding

The polar code has been chosen for the control channel in the 5G new radio (NR), because it can fix errors well, even at a low signal-to-noise power ratio. Its performance is found to get close to the Shannon limit for long frame lengths. This paper shows an FPGA (Kintex-7, Xilinx part number XC7K325T-2FFG900C) implementation of Polar codes that use the successive cancellation (SC) algorithm. The SC decoding algorithm of Polar Code is optimized to make it more practical. It is found that using fewer bits to represent the log-likelihood values (LLR) in the decoder has a significant effect on the used silicon area and throughput, without a significant effect on the performance. Different simulation tests are carried out over the Additive White Gaussian Noise (AWGN) channel to prove the effectiveness of the proposed scheme. The arbitrary-precision data types that Vivado High-Level Synthesis (HLS) offers are used instead of the more expensive float representation to reduce the latency and utilized resources. The results show a reduced latency of about 76% and a noticeable decrease in logic elements and DSP units (DSP48E) by about 50% and 86%, respectively. The hardware run of different polar coded systems with an arbitrary precision instead of float data type reveals a shallow degradation in performance.