A Multi-Core Verification Method of Vector Instructions Based on Spike

Verifying the instruction execution against a golden execution model following the ISA is becoming a common practice to verify processors. This method plays an important role in the single-core verification scenario. However, for the correctness monitoring of multi-core processors, the uncertainty caused by shared storage makes the above method unable to meet the requirements better. This paper provides a multi-core function verification scheme of vector instructions based on RISC-V architecture, which monitors the instruction execution time of DUT and triggers the reference model in time through Test Bench. This scheme uses Spike, the instruction set standard implementation model specified by RISC-V Foundation, as the reference model of verification environment. It adds a DPI (Direct Programming Interface) interface for the simulation environment to call, modifies the execution mechanism of vector instructions in Spike's existing model, and then triggers the synchronous execution of Spike with the time of the instruction monitored from each core in the DUT (design under test), and finally compares the execution results of the DUT and Spike. From the top level, although there is no adjudication mechanism for the order of multi-core access data in Spike, the time of data acquisition or update of each core is exactly the same as that in the DUT. So that the multi-core comparison verification of vector instructions can be completed in the simulation stage, and more bugs such as vector instructions and multi-core consistency can be found earlier.