Soft-error Tolerance by Guard-Gate Structures on Flip-Flops in 22/65 nm FD-SOI Technologies

We evaluated soft-error tolerance by heavy-ion irradiation test on three-types of flip-flops (FFs) called the standard FF (STDFF), the dual feedback recovery FF (DFRFF), and the DFRFF with long delay (DFRFFLD) in 22/65 nm FDSOI technologies. The guard-gate (GG) structure in the DFRFF mitigates soft errors. An SET pulse is removed by the C-element with the signal delayed by the GG structure. DFRFFLD increases the GG delay by adding two more inverters as delay elements. We investigate the effectiveness of GG structure in 22 nm and 65 nm. In 22 nm, Kr (40.3 MeV-$cm^{\mathbf{2}}$/mg) irradiation tests revealed that DFRFFLD has sufficient soft-error tolerance in outer space. In 65 nm, the relationship between GG delay and CS reveals the GG delay time which no error was observed under Kr irradiation.