Fault Propagation in Microprocessors with Configurable Cache Memory

Commercial-off-the-shelf (COTS) microprocessors are attractive in applications with radiation requirements because they have better capabilities than radiation hardened microprocessors. This work reports the single event functional interrupt SEFI cross-section $\sigma$ of a configurable single-core microprocessor. The relationship between the performance of the software algorithms and their SEFI cross sections is reported. During irradiation, the cache configuration was changed between on and off states. When the cache was activated the SEFI $\sigma$ increased, but the work completed by the processor before a SEFI was at least $1.5 \times$ greater compared to the work completed when cache was off. The software algorithms with the highest SEFI cross section had the lowest time performance gain when cache memory was on, and they had the lowest percentage of L1 instruction cache hits.