A Global-Local Feature Multilevel Fusion Network for Chip Defect Segmentation

In the chip encapsulation process, internal defects arise due to both natural and anthropogenic factors, primarily manifesting as a diverse array of missing Gold Wires and Solder Joints. Accurate delineation of these Gold Wires and Solder Joints through a mask is essential for defect analysis. Notably, Gold Wires exhibit a large spatial scale, while Solder Joints have a smaller scale; both possess intricate textures. Although Transformer methods can effectively model relationships between distant pixels, they tend to lose fine-grained texture information. Conversely, CNN methods excel in learning local information but may compromise spatial relationships between targets. Consequently, utilizing either of these methods alone presents limitations. In addressing this issue, we propose the Global-Local Feature Multilevel Fusion Network architecture—SegCAF, which combines the strengths of CNN and Transformer. Our research introduces a dual-branch interactive parallel network, where the CNN branch extracts local information, and the Transformer branch captures global dependencies. Subsequently, a feature fusion module aligns and aggregates the encoded features from both branches, leveraging both global context and local details. Furthermore, an auxiliary segmentation head is added to the Transformer branch to enhance training efficiency and reinforce information interaction between the two branches. In the experimental phase, we collected and annotated a dataset of X-ray images depicting internal defects in industrially produced chipsets. We conducted feature visualization analysis and model performance evaluations on this dataset. The results demonstrate that the proposed SegCAF model significantly outperforms existing mainstream models, achieving an mIoU of
$90.56\%$
and an mPA of
$81.17\%$
. This indicates that SegCAF effectively addresses the challenge of precise segmentation of chip defects using both local and global information in network design and optimization. Consequently, it enhances the quality of relevant electronic products and improves production inspection efficiency.