Parasitic Gate Capacitance Model for N-Stack Forksheet FETs

The gate-all-around nanosheet (NS) field effect transistors (FETs) are hailed as the most promising candidate for scaling the CMOS technology beyond the 5-nm technology node owing to their enhanced electrostatic integrity. However, the fabrication process dictates the minimum spacing between the PFET and NFET (PN margin) in the NSFET architecture and limits the scalability of the PN margin. Therefore, the forksheet (FS) FET architecture with PFET and NFET separated by a dielectric wall was proposed to minimize the standard cell height from six Track length of M1 (6T) to 5T. Furthermore, the FSFETs exhibit comparable static performance to the NSFETs while providing significant improvement even from a fabrication perspective. Although the FSFETs are expected to show a better dynamic performance owing to the reduction in the Miller capacitance, vertical stacking of FSs may lead to an increase in the parasitic capacitance and degradation in the overall system performance. Moreover, the dielectric wall may induce severe electrostatic coupling between the NFET and PFET. Therefore, it becomes imperative to analyze and formulate an analytical model for the parasitic capacitance components of the FSFETs. To this end, in this work, for the first time, we have developed analytical models for different parasitic gate capacitance components of
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-stack FSFETs and analyzed the influence of various structural parameters on the total parasitic gate capacitance of two architectures: split gate (SG) and merge gate (MG) FSFETs. The results of the developed analytical model overlap with the results extracted from TCAD simulations validating the accuracy of the proposed model.