Design and Research of Parallel Data Transfer Between Domestic RISC-V Soft Core and FPGA

FPGA localization is the road to independent control, because of the late start, the domestic soft-core CPU function is not perfect, such as soft-core CPU only supports serial transmission, and FPGA logic layer can not be parallel data transmission. In this paper, we use the domestic FPGA platform of Anlogic Technology, based on the RISC-V soft core of Anlogic, complete the design of AHB-lite bus, analyze the timing of reading and writing dual-port RAM on AHB bus, and complete the design of dual-port RAM controller based on the AHB bus protocol, and finally, through the simulation, we prove that the RISC-V soft core can read and write the parallel data of FPGA logic layer correctly through the AHB-lite bus.