A Study on The Impact of Lot Priorities on Cycle Times In Semiconductor Manufacturing

This paper presents a study on the impact of lot priorities on their cycle times in a workshop within a wafer manufacturing facility using simulation. We have specifically analyzed the waiting times of lots and the associated speed up or speed down. Computational experiments were conducted using Anylogic 8 based on industrial instances from the site of Crolles of STMicroelectronics. Results indicate that a speedup of more than 300% for high-priority lots and a speed down of less than 10% are achievable when the proportion of high-priority lots remains below 10%. This study initiates a first step towards a better priority mix management, which is critical in the semiconductor manufacturing industry.