Co-Designing Hardware/Software to Protect Crypto-Chip Side Channel Analysis at Design Time

SCA is an influential method used in physical cryptanalysis. Generally, the assessment of SCA security is carried out post-production in typical industrial procedures. This post-production analysis, however, is prone to errors, costly, and time intensive. Thus, to heighten efficiency, it has been proposed to carry out SCA analysis during design-time, drawing inspiration from the ethos of hardware/software co-design. This paper first introduces the limitations of traditional embedded system software/hardware design and the process of software/hardware co-design and a general SCA leakage model, followed by an overview of the process behind a design-time security analysis. Next, we establish a versatile simulation and analytical framework to evaluate various SCA leakages. In conclusion, we provide a demonstrated experiment that carries out a design data SCA analysis for the crypto-chip integrated having an AES-128 core.