Performance Analysis of FIR Filters using High Speed VLSI Adders for FECG monitoring

Cardiac disorders are common in fetus which when diagnosed at the early stages may eradicate the aftermath crisis as an adult. The determination of such disorders shall be diagnosed using placement of surface electrodes through computer-aided design. In order to detect anomaly during labor in Fetal Electrocardiogram signal(FECG), although there are monitoring equipment in place, they will regretfully imbibe noise to the observations recorded. Consequently, the purpose of the paper is to in general review the FIR filters implemented with various high speed VLSI adders to eliminate noise sources during FECG signal extraction. The simulations were conducted using MIT- BIH Arrhythmia using Xilinx ISE 9.1, MATLAB 2013b, ModelSim 10.0b, and Cadence Virtuoso under 90nm process file and is analyzed that the efficiency of High Speed DEC Alpha adder is 90.01% which is 19.6% better than the existing Carry Save Adder (CSA). The overall filter efficiency is estimated as 97.1% for DEC based adders with minimal glitch rate of 0.69% with an average when analyzed for all noise sources.