SiC MOSFET High Side Gate Driver Design Using HV CMOS Process

High side driver is one of major factors determines the performance of SiC MOSFETs. This research proposed an AGD (active gate driver) design that uses a window comparator circuit, feedback-controlled split-path circuit, and tri-state inverting buffer to generate weak and strong driving signals. The proposed AGD has been implemented in TSMC
$0.18-\mu \mathrm{m}$
HV CMOS (TI8HVG2) technology, which has a core area of 3200 x 2632
$\mu \mathrm{m}^{2}$
and an overall chip area of 4515 x 3260
$\mu \mathrm{m}^{2}$
. The HV MOS and diode model of Infineon IMW65R048M1H are used as the power MOSFETs in all-PVT corner post-layout simulations. The peak gate current (
$\mathbf{I}_{g(pk)}$
), rise time
$(\mathbf{t}_{ris{e}})$
, fall time
$(\mathbf{t}_{fall})$
, and average power consumption (
$\mathbf{P}_{ave}$
) for the worst corner are 4.15 A, 153 ns, 187 ns, and 32.7 W, respectively, at
$\mathbf{f}_{PWM}=500$
kHz.