A High-PSR Wide-Load Capacitor-Less LDO with Back-Gate Control Technique in 22-nm FD-SOI

This paper presents a wide-load range, high PSR, area-efficient, capacitor-less low-dropout (LDO) regulator design along with a novel back-gate control technique (BCT). The BCT improves the LDO loop gain by controlling the back-gates of the transistors, which would have otherwise experienced headroom issues stemmed from various load current conditions. The proposed LDO achieves a wide-load current range between 0 and 100 mA, maintaining a stable power supply rejection (PSR) of 70 dB at 1 kHz. It contains an on-chip output load capacitor of 17 pF and can provide an output voltage range of 750 mV to 950 mV with 1.6 mV resolution. The line regulation value is 3.080 mV/V while the load regulation is 0.032 mV/mA. It consumes 0.010 mm
²
of active silicon area. The suggested LDO is designed and characterized in a 22-nm FD-SOI technology,