Randomized Bulk-Voltages: A Countermeasure to Mask Side-Channel Leakage of CMOS Logic Gates

Integrated Cryptographic Circuits implemented in Complementary Metal Oxide Semiconductor (CMOS) technology have proven to be vulnerable to static power analysis attacks. In this paper we explore the limitations of a countermeasure against leakage based power analysis attacks called Exhaustive Logic Balancing, which demonstrates complete input-independence in ideal simulations but loses it in the presence of mismatch. We propose a solution to address this input-dependency by introducing input-independent noise through randomized variations in the bulk-voltages of the logic gate's internal transistors. Simulations show that this method can conceal input-dependency in the power consumption by introducing noise with a larger magnitude than the variations in current caused by mismatch, and thus decreasing an attacker's signal-to-noise-ratio significantly in the event of a power analysis attack.