A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration

A fully synthesizable dynamic voltage comparator with time-domain offset calibration is proposed. By utilizing a pulse-width adjustable signal to control tri-state buffers, a compensation voltage is generated for offset cancellation in time-domain, which achieves high calibration precision with modest implementation overhead, in addition to great suitability to advanced CMOS process. The whole circuit, including the comparator core and the offset calibration module, is designed with digital standard cells and does not require dedicated compilers. All components are fully synthesizable and the layout is generated automatically through the digital synthesis in the 28nm CMOS process, occupying an area of 33x33um
²
. Monte-Carlo simulations show that the proposed calibration reduces the standard deviation of the comparator offset from 15.25mV to 0.92mV.