Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications

FPGAs are widely used in various applications such as communications, digital signal processing, and artificial intelligence. As a basic arithmetic unit in these applications, the multiplier's optimization can significantly improve hardware efficiency and performance. This paper proposes an optimized unsigned Booth multiplier by leveraging the hardware feature of FPGA, decreasing 36.4% and 45.5% in the area over the Xilinx LogiCORE multiplier and the Xilinx Synthesis Default, respectively. Additionally, an approximate unsigned multiplier with probabilistic analysis compensation is proposed. The error compensation scheme is implemented by the FPGA's carry chain without additional resource consumption. This design saves 34.8 % area compared to the state-of-the-art paper with higher precision. The bit error rate deterioration of the proposed multiplier is less than 0.0008 when applied to a 5G MIMO wireless communication receiver.