A High-Performance Digitally Programmable FVF-Based LDO for Efficient Power Management in Driving Distributed Loads Using a Shared Power Grid

Modern System on Chip (SoC) seeks multiple LDOs to provide regulated supply to its different peripherals. However, distributed LDOs across the chip increase power consumption and at the same time, each driver requires a separate transient detection block to reduce the undershoot/overshoot, increasing the area. The work presents a viable solution to tackle such issues by proposing a Multi-loop LDO that uses distributed Flipped Voltage Follower (FVF) drivers. The topology presents one central unit common to every distributed FVF driver across the chip that acts as a global loop, whereas each FVF loop serves as a fast local loop. The proposed power grid structure reduces the overshoot/undershoot voltage without adding additional transient detection schemes. The work depicts design and simulation results to validate the proposed idea with four distributed drivers in 180 nm TSMC node. Simulation results show that the proposed technique helps reduce the droop voltage by more than 40% compared to conventional structures without increasing the design complexity.