PLL-SAR: A New High-Speed Analog to Digital Converter Architecture

A novel, high bandwidth Phase-Locked-Loop Successive Approximation Register (PLL-SAR) ADC topology is proposed. To ensure fast loop settling without power hungry TDCs, non-linear settling is exploited. A major advantage of the PLL-SAR is its ability to achieve relatively high resolution without the need for VCO linearity calibration. Simulations of the proposed PLL-SAR ADC in a 22nm FinFET process showed a bandwidth of 13MHz with 1.41mW power consumption for a linearity of 8 bits.