An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS

This paper presents an 8-GHz octa-phase clock corrector employing a shared clock selector-based digital delay-locked loop (DLL). The corrector performs two functions: Octa-phase Error Corrector (OEC) and Duty-Cycle Corrector (DCC). The phase error is detected via the 3T/8 delay line and the duty-cycle error is detected by utilizing opposing polarity edges in a differential clock without the use of an additional delay line. An Edge Converter (EC) is designed to match the edge propagation delay through an 8:1 MUX and an EC to achieve a high level of accuracy in duty-cycle calibration. Furthermore, to save power and area, a clock selector composed of a multiplexer (MUX) and a logic generator is shared between phase and duty-cycle error detection loops. The prototype chip has been fabricated in 40-nm CMOS technology occupying an active area of 0.047 mm
²
. The total calibration power consumption of the corrector is 17.1 mW at 1.0-V supply.