Electrical and Physical Evaluation of Logic Network Generation Methods for SCCG

The digital integrated circuit implementation strategies in the microelectronics industry have changed over the years considering the design costs. Hand design flows have been replaced by Electronic Design Automation (EDA) tools that automate the integrated circuit design process. However, implementing ICs through the traditional standard cell flow does not ensure power and area optimization because cell libraries have a limited number of logical functions. Therefore, research has shown that using the Static CMOS Complex Gates (SCCG) approach can lead to electrical and physical improvements. This paper investigates the impact of three netlist optimization methodologies (FAC, FAC-PD, and BDD) on power dissipation, number of transistors, area, and wirelength when applied to 180nm CMOS TSMC technology. The study shows that the FAC method is the most suitable for a design-on-the-fly flow when using the SwitchCraft framework since it optimizes the number of transistors, power consumption, layout area, and wirelength,