Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips

Artificial intelligence (AI) edge devices are highly susceptible to memory wall issues imposed by the von Neumann computing architecture. Non-volatile on-chip computing-in-memory (nvCIM) is a viable approach to reducing energy consumption and latency in AI edge devices by reducing the movement of intermediate data between the memory and computing unit. This paper presents an overview of nvCIM macro structures., including in-memory computing (IMC) and near-memory computing (NMC), as well as challenges in the design of these devices. This paper also assesses the performance of recent silicon-verified nvCIM macros and the challenges that lie ahead.