Challenges on Design and Technology Co-Optimization: Design Automation Perspective

This paper surveys a number of noticeable recent research activities on the design and technology co-optimization (DTCO) in design automation perspective in conjunction with the exploration of standard cells. As the technology node advances, it is utmost important to enhance EDA tools as well as to explore and find a standard cell architecture that is best suited to the target design, in terms of performance, power, and area (PPA) metrics of the resulting chip. Specifically, the DTCO activities surveyed in this paper are (1) the state-of-the-art automatic cell layout generators, which are essential vehicle for DTCO, (2) DTCO utilizing multi-bit flip-flop cells by selectively debanking or resizing cells to resolve timing closure problem, (3) DTCO supporting the designs with cells of heterogeneous heights, and (4) DTCO considering the vertical alignment mismatch between cell gate poly and metal pitches in advanced nodes.