Design and Performance Analysis of 11-T SRAM Cell with BTI Reliability

The standard 6T SRAM cell stability decreases due to diminished size. The challenges in 6T SRAM are power consumption high, more delay and noise margin in static state low package density. The 11-T cell can be used at low supply voltages but similar operation of writing as of 6T cell and the major disadvantage is its read/write access delay and more area. In order to enhance the write operation of SRAM cells and address the limitations associated with the 11-T cell configuration, two novel 11-T SRAM topologies are currently under development. These topologies involve the incorporation of supply-cut-off and ground-cut-off techniques. However, as the physical distance between transistors decreases, there is a heightened risk of multi-bit soft errors or upsets occurring within the cell. To mitigate this issue, the Bit Interleaving Architecture is being employed. One of the principal reliability concerns in this context is Bit Temperature Instability (BTI). Strategies to mitigate the impact of BTI in MOS transistors include improving the threshold voltage. The implementation of these advanced 11-T SRAM cell designs promises several benefits, including improved write/read margins, reduced leakage power, increased operational speed, and decreased write/read power consumption. Comparative assessments are being conducted with both 6T and conventional 11-T SRAM cells to validate these improvements.