An 8-bit 100 kS/s Low Power SAR ADC with Modified EPC for Bio-Medical Applications

Successive Approximation Register (SAR) ADCs are used for low-power applications because of their energy-efficient architecture. SAR ADC is suitable for low-power applications because of its simple SAR logic, Capacitive DAC (CDAC) architecture, and it can be easily portable to newer technology nodes. SAR ADC can be used for biomedical applications, especially in pacemakers. The major building blocks of SAR ADC are sample and Hold circuit (S/H), Comparator, DAC, and SAR Control logic. The main power-hungry module of the SAR ADC is the comparator. The accuracy and energy efficiency of the SAR ADC solely depends on the comparator architecture. Hence, the design of a power-efficient comparator is crucial for the design of SAR ADC. This work presents an 8-bit, charge re-distribution SAR ADC architecture with a modified low-power Edge-Pursuit Comparator (EPC), which is designed and simulated in Cadence Virtuoso 180 nm UMC CMOS technology with a supply voltage of 1.8 V and a sampling rate of 100 kS/s. It is observed that the proposed SAR ADC with modified EPC consumes a power of about 0.05 mW for 390.625 Hz signal frequency. The proposed ADC achieves a simulated SNDR of 48.21 dB, SFDR of 54.94 dB, and ENOB of 7.71 bits respectively for a 390.625 Hz signal at 100 kHz sampling frequency.