A High Speed 32-bit Approximate Adder with Improved Accuracy

Approximate computing has gained quite some research attention in the last few years. In the recent techniques developed in this domain, a trade-off between accuracy and design metrics, such as delay, power and area has been observed. Our prime purpose is to reduce the value of the design metrics without sacrificing excessive accuracy of the concerned adder. In this paper, firstly two novel 32-bit approximate adders are proposed, then a comparative study is performed with some already existing adders. We portray a wide comparison based on both conventional and approximate design metrics. The proposed adder provides almost a 57.6% decrease in time delay than the conventional Ripple Carry Adder with a small trade-off of accuracy. This adder makes use of already existing approximate adders to optimise its metrics. The designs have been verified and tested on ASIC using UMC 65 nm technology on Synopsys and on Digilent Basys3 FPGA board.