Design of High PSRR and Low Noise for LDO

In this paper, a Low Dropout Regulator (LDO) with high Power Supply Rejection Ratio (PSRR) and low noise is designed based on the SMIC 40nm CMOS process. The PSRR of the LDO is improved by adding feed-forward ripple cancellation (FFRC) technology between the supply voltage and the gate of the power transistor so that the gate-source voltage V
GS
of the power transistor is not interfered by the power supply ripple; the error amplifier adopts a source negative feedback structure and a BJT pre-amplification stage to reduce the noise. With an output voltage of 1.5 V, the PSRR is 100 dB at low frequency and 60 dB at 10 KHz; the output noise is 0.1 μV at 1 KHz, and the integrated noise is about 15.91 μV in the range of 10 Hz ~ 100 kHz.