A 20.3μW 1.9GΩ Input Impedance Capacitively-Coupled Chopper-Stabilized Amplifier for Bio-Potential Readout

This paper presents a low-power chopper-stabilized capacitively-coupled frontend amplifier with auxiliary-path-based input impedance (
${Z} _{\mathbf {in}}$
) boosting. In order to achieve a high
${Z} _{\mathbf {in}}$
, a low noise and a small chip area, techniques on both system level and circuit level are implemented. On the system level, small capacitors (
${C} _{\mathbf {in}}$
= 0.5 pF,
${C} _{\mathbf {fb}}$
= 25 fF) are used with a biased pseudo-resistor (
${R}$
= 2.5
$\text{G}\Omega $
) fed back to an amplifier internal node. As a result, a high achievable
${Z} _{\mathbf {in}}$
and low high-pass corner frequency are achieved. On the circuit level, an input capacitance shielded current feedback (CSCF) topology achieving effective 10 fF
${C} _{\mathbf {amp}}$
is proposed as the core of the capacitive feedback amplifier in order not to increase the input noise. Moreover, the design space of auxiliary-path-based boosting is explored to obtain the optimal value of buffer bandwidth and auxiliary capacitor size to save power. The amplifier and its
${Z} _{\mathbf {in}}$
boosting circuit are implemented in a standard 55 nm CMOS process and characterized experimentally. Measurement results show that the proposed amplifier provides an input noise density of 50 nV/
$\surd $
Hz, and an integrated noise of
$0.85~\mu $
Vrms in 200 Hz band. The
${Z} _{\mathbf {in}}$
is boosted to 1.92
$\text{G}\Omega $
at DC and 1.02
$\text{G}\Omega $
at 50 Hz with only
$1.0~\mu \text{A}$
in each auxiliary path buffer. The amplifier also archives 77 dB CMRR and 76 dB PSRR while consuming
$20.3~\mu \text{W}$
in total.