A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning

This brief presents a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28 nm CMOS technology and uses pipelined structure to have high resolution at the same time. In the adopted sample-and-hold amplifier-less (SHA-less) pipeline, a comparator-based correction method is proposed to solve the associated aperture error in the frontend stage where input is sampled at the latch node. By tunning the path bandwidth, rather than using delay line in comparator clock path, the output spreading related to aperture error is reduced by the proposed tunning method to offset-limited level up to 4 GHz input frequency. The modified reference buffer in the ADC reuses the existing transconductance and improves its power efficiency when driving the pipeline stages. Buffers and digital calibrations are implemented on-chip to help wideband high-speed operation and to correct non-idealities in analog circuits. The fabricated ADC chip achieves 59.7 dB SNDR, 60.3 dB SNR and 69.3 dBc SFDR at 1.95 GHz input frequency. The input bandwidth is above 5 GHz. ADC power consumption is 782 mW, resulting in 247.8 fJ/conv.-step
${\rm FoM_{W}}$
and 153.7 dB FoMS.