A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm

A 24–28-GHz sub-50-fsrms jitter fractional-
$N$
charge pump phase-locked loop (CPPLL) is presented in this work. A dual-digital-to-time converter (DTC)-assisted time-amplifying phase-frequency detector (TAPFD) structure is proposed to suppress the in-band noise of charge pump (CP) and cancel the quantization error (QE) simultaneously while keeping low power consumption. Moreover, a cascadable DTC gear estimation and nonlinearity compensation algorithm (NLC) is also proposed to mitigate the fractional spur. The presented PLL achieves a measured integrated rms jitter including spurs of 37.1 fs with −255.2-dB FoM
$_{J}$
for integer-
$N$
channel and 45.6 fs with −253.0-dB FoM
$_{J}$
for fractional-
$N$
channel.