Device Feasibility of 60-nm-Scaled Vertical-Channel Memory Transistors Using InGaZnO Channel and ZnO Charge-Trap Layers

A 60-nm channel length vertical-channel charge-trap memory (V-CTM) using oxide semiconductor channel was demonstrated for advanced memory applications. Mesa-type vertical channel was well implemented to reduce cell footprint as well as vertical distance. The fabricated V-CTM exhibited a memory window (MW) of 7.7 V between the program and erase states with simple incremental step-pulse programming (ISPP) scheme, verifying the facile erase capability of the designed V-CTM. There was not any marked degradation in device parameters with scaling the channel length from 300 to 60 nm. Long retention time (>108 s) and robust endurance (>104 cycles) were also secured. Four-level multistates could be assigned with ISPP.