A Reconfigurable Step-Down Switched-Capacitor Power Converter Using Optimized Partial Series-Parallel (OPSP) Topology

This brief presents a reconfigurable step-down switched-capacitor power converter fabricated using a 180 nm CMOS process for low-power applications. The proposed Optimized Partial Series-Parallel (OPSP) topology aims to achieve an intermediate voltage conversion ratio while more effectively minimizing parasitic capacitor losses. This improvement is realized by eliminating one of the flying capacitors, specially the one responsible for the largest parasitic capacitor voltage swing, distinguishing it from the previously reported Partial Series-Parallel (PSP) topology. Furthermore, the use of NMOS capacitor in conjunction with flying parasitic junction capacitors is also proposed to enhance the capacitor density. This switched-capacitor power converter is capable of delivering a 1.8 V output within an input voltage range spanning from 3.1 V to 4.1 V. Employing the methods outlined in this brief enables the attainment of a peak power conversion efficiency of 83.1% when the load current is 1.8 mA.