Layout Design for DNTT-Based Organic TFTs Considering Fringe Leakage Current

Dinaphtho[2,3-
$b$
:
$2'$
,
$3'$
-
$f$
]thieno [3,2-
$b$
]thiophene (DNTT) is recognized for its excellent carrier mobility and stability, which makes it a popular choice for p-type organic semiconductors (OSCs) in thin-film transistors (TFTs) for flexible electronics. Practical applications of DNTT-based organic TFTs (OTFTs) have revealed that their leakage currents are significantly layout-dependent. In this article, we propose and evaluate three OTFT layouts with different layer–contact combinations to assess the leakage current characteristics. Among the proposed layouts, two exhibit noticeable leakage currents, one in the gate insulator and the other in the OSC fringe; the third layout successfully reduces these leakage currents. Our results indicate that the layout exhibiting the fringe leakage current is well suited for use as a pseudo-resistive device with tunable resistance, while the layout with the high ON–OFF current ratio is suitable for use as a switching device. Based on our measurement results, we propose a fringe leakage current model for designing efficient OTFT circuits. We analyze the transfer characteristics of pseudo-CMOS logic gates with various pull-down network layouts to demonstrate the application as a pseudo-resistive device. Our results show that the pull-down network with the pseudo-resistive device effectively controls the output voltage swing, thereby enhancing the stability of OTFT-based circuits.