A High-Performance, Low-Temperature Self-Aligned Gate E/D Process

A high-performance, LDD SAGFET E/D process using a substitutional gate, a spacer and arsine over-pressure annealing has been developed. The gate metal is formed at a low temperature after post implantation annealing. Transconductance of 240 mS/mm and K factor of 4.4 mS/mm for 1.4×20 micron E-SAGFET with Vp=+0.1V and a 32 mV std. dev. over a 3" wafer has been demonstrated. An ECL compatible gate array having 561 four-input NOR gates has been developed. Full functionality of 8X8 multiplier, 8-bit MUX and DEMUX, 8-bit adder and divider have all been demonstrated in personalized gate arrays. Fully loaded internal gate delay of 225 ps with 1.5 mW dissipation and 5 ns 8×8 multiplication time have been realized using 1.4 micron gate. Unloaded gate delay of 110 ps was demonstrated with 1.25 micron gate. The E/D technology was based on a conservative, planarized two-level metalization using silicon nitride as an interlayer dielectric. Such ECL compatible E/D gate array products will be made available in the near future.