Study of Poly-Si Gate Annealing on the Electrical Characteristics of 1200 V 4H-SiC MOSFETs

1200 V 4H-SiC MOSFETs were successfully fabricated on 6-inch wafers with an on-resistance of 34 mΩ. Following 60 min annealing at 900°C of the phosphorus-implanted poly- Si gate, the on-resistance of the SiC MOSFET decreases, but the threshold voltage and breakdown voltage of the device also decrease. Additionally, CV testing revealed a reduction in interface state density after poly-Si gate annealing. Through TCAD simulations, we observed that the decrease in interface state density can be attributed to the diffusion of phosphorus atoms into the SiO
2
/SiC interface.