Implementation of 1200V SiC MOSFET with 20% Lower On-Resistance by Designing the Interrupted P+ Region

Although the SiC MOSFETs with square or hexagonal designed cells have a small on-resistance, the electric fields of sharp corners within these designed cells lead to the reduction of blocking voltage. The SiC MOSFETs with linear cells can maintain the blocking voltage, while the relatively large cell usually increases the on-resistance and power consumption. In this article, we designed and fabricated the SiC MOSFETs with linear cells and interrupted linear cells whose N
⁺
region is embedded with the P
⁺
region. Then we compare their characteristics of specific on-resistance, forward characteristic, and blocking voltage, and report the demonstration of a high-voltage 4H-silicon carbide (SiC) MOSFETs with 20% losses of on-resistance by interrupting the N
⁺
region with P
⁺
region. We provide a new linear cell design that can effectively reduce the on-resistance of 1200 V SiC MOSFET and maintain the blocking voltage.