A Short Channel Self-Alignment Process for High-Voltage VDMOSFETs in 4H-SiC

Short channel is an effective method to reduce the channel resistance, which accounts for a large proportion of the total resistance due to the high interface state of the gate oxide for 4H-SiC VDMOSFET. The self-aligning processes were developed to obtain the different channel lengths smaller than 1 μm for MOSFET in this paper. Following the P-well ion implantation with an SiO2 film as a mask, multiple thicknesses of oxide film are grown by PECVD or LPCVD. Then 0.5μm, 0.6μm, 0.7μm side walls are accessed by dry etching process. The results of the SEM test showed that the intra-wafer uniformity variances are 8.06%, 4.48% and 4.71% for the 0.5μm, 0.6μm, 0.7μm channel, respectively. And the electrical test results show that the device resistance decreases by 50% when the channel size is reduced from 0.7um to 0.5um.