Influence of Fin Configurations on the GaN HEMTs under High-Voltage Bias

As the demand for high-performance high-electron mobility transistors (HEMTs) increasing, fin configurations have become crucial for improving device performance. Nevertheless, there are few researches on the reliability of Fin-HEMTs under high-voltage bias. In this article, we have explored the influence of fin configurations on the electric field distribution of GaN-based HEMTs under high-voltage operating conditions through Silvaco TCAD simulation, thereby determining the locations of the failure points with one located at the middle surface of the barrier layer near the gate edge close to drain and the others located at the side gate feet near the drain. Furthermore, through comprehensive consideration of the influence of fin configurations on the high field performance and reliability of the devices, it is concluded that within a certain range, the smaller fin width (W
_Fin
) and larger fin height (H
_Fin
) generate smaller peak electric field strength. Moreover, W
_Fin
has a great impact on the electric field strength of the barrier layer while H
_Fin
has a great impact on that of the buffer layer. In general, these conclusions provide guidance for commercial device design.