High-Performance Time-to-Digital Converter IP-Core for Xilinx Ultrascale/Ultrascale+ FPGAs

In this contribution, we present the implementation of a tunable, high-performance and multi-channel Time-to-Digital Converter (TDC) IP-Core for Xilinx Ultrascale/Ultrascale+ Field Programmable Gate Arrays (FPGAs). The concept of tunability refers to the user-friendly graphical user interface (GUI) of the IP-Core, which allows to easily set the resolution (LSB), the Full-Scale Range (FSR), and the number of channels of the device. In particular, we can tune the LSB up to hundreds of femtoseconds and the FSR up to some days. Moreover, the TDC presents a maximum measurement rate up to hundreds of Msps per channel, satisfying the high count-rate capability requirement of state-of-the-art detectors. To obtain such an high-resolution over a wide FSR, the measurement is performed according to the Nutt-Interpolation technique, in which the timestamp of each channel is made by a coarse part and by a fine part. The high-resolution given by the fine part is obtained from the Super Wave Union (SuperWU) sub-interpolation algorithm, which implements a tunable number of TDLs working in parallel, each one with an also tunable number of taps. This generates a Virtual-TDL (V-TDL) composed by virtual-taps, whose propagation delays are faster than the real ones of the single-TDL. From the design point of view, the TDC has been implemented and fully tested on a Kintex Ultrascale FPGA, hosted by the KCU105 Evaluation Board, where the TDLs have been obtained by cascading CARRY8 primitives available into the fabric of the Xilinx device. We managed to obtain up to a few dozen of channels.