Digital SiPMs in a 110 nm CMOS Technology with Fast Parallel Counter Architecture

This paper presents the design of a digital silicon photomultiplier (dSiPM) in a 110 nm CMOS technology. The detection pulses, generated by an array of single photon avalanche diodes (SPADs), are simultaneously read out in real time by means of a fast parallel counter, which was designed using a purposely developed algorithm. The problem of spurious pulses (glitches), generated during the counting operation, was strongly mitigated by equalizing the internal propagation delays. A balanced symmetric full adder was designed for this purpose. Dedicated circuits devoted to the rejection of individual dark pulses and to the implementation of a signal over threshold (SOT) logic have been included in the structure.