High-Rate Handling Solution for Multiple Channels, FPGA-Based, Time-to-Digital Converters

With the increasing complexity of applications, the demand of high-counts number of channels for Time-to-Digital Converters (TDC) has grown, creating the issue of handling multiple timestamps contemporaneously. In this contribution, we will present the BeltBus (BB), a solution that is able to handle several TDC channels and can reach a measurement rate of several hundreds of Msps. Moreover, BeltBus temporally orders the incoming timestamps to reduce the computation effort of the following elaboration modules; e.g., time-taggers and histogrammers. Finally, the Beltbus allows to have an high dynamic range and an high resolution without having routing issues in the FPGA.Theese tasks are performed thanks to several cascaded IP-Cores(Node Inserters), which are responsible for the comparison of a TDC channel timestamp with the output from the previous node and for sending out the lowest one. This means that each node has 2 inputs and 1 outputs, except for the first one, which has only the input from the TDC. This architecture, with respect the calssical parallel one, allows to have a modular design suited to support a very high number of channels. Indeed, the BeltBus is capable of handling hundred of channels with overall data rate (DR) of several Msps at the state-of-the-art.The whole system has been tested on a 16 channels TDC made with an Artix-7 Field-Programmable Gate Array (FPGA) clockied at 100 MHz, wich has a resolution of 1 ps and a FullScale Range (FSR) of 10.3 s. With this setup an overall DR of 98.3 Msps has been obtained, obtaining a transmission efficiency of 98.3%.