A Low-Dead-Time FPGA-Based Time-to-Digital Converter Employing Resource-Efficient Downsampling-Multiplexing Encoding and Dual-Histogramming for LiDAR Applications

This article presents a low-dead-time resolution-adjustable time-to-digital converter (TDC) employing resource-efficient downsampling-multiplexing (DS- MUX) encoding and dual-histogramming based on field-programmable gate array (FPGA). By adopting the proposed DS-MUX encoding, multiple transition edges in the delay line that are triggered by different echo events can be processed simultaneously within one clock cycle, which excels traditional thermometer-to-binary encoders. By employing the proposed block random-access memory (BRAM) based dual-histogramming module with unique address remapping, the histogramming throughput is improved while invalid timestamps are removed with the help of a coarse accumulator. In addition, bin decimation and bin-width calibration are applied to enhance linearity and precision. Implemented on a 28-nm FPGA, the proposed TDC reduces the dead time to 0.59x clock cycle and thus improves the conversion rate by 1.7x. More importantly, the proposed TDC only consumes 402 look-up tables, 588 flip-flops and 2.5 BRAMs. To the best of our knowledge, this is the first resource-efficient FPGA-based TDC that reduces dead time to below one clock cycle with BRAM-based histogramming for multichannel light detection and ranging applications.