Static Timing Analysis Method for Reconfigurable SoC with Various Types of Routing Resources

Reconfigurable systems on a chip (RSoC) routing tree architecture consists of both digital elements and MOS switches. To evaluate the performance of routed integrated circuits (ICs), a netlist and a library of characterized elements is required. However, the MOS switch is an analog element and models for describing the time parameters of digital cells, including the non-linear delay model, cannot be applied to it. To solve this problem, this paper proposes a method for estimating the ICs performance based on the use of the connections equivalent electrical capacity and proposed formulas for calculating time parameters. The formulas were obtained as a result of researching the dependence of circuit timing characteristics on three parameters: the number of pass switches in the net, the load capacitance and the parameters of transistors at the output stage of the routing element. The approach allows to calculate the output signal parameters for various types of RSoC routing elements, including pass transistors, without critical losing of accuracy.