Mitigating Non-ideality Issues of Analog Computing-In-Memory in DNN-based designs

Analog Computing-in-memory (ACIM) has emerged as a promising approach to enhance energy efficiency and throughput in matrix-vector multiplications (MVMs) for deep neural network (DNN) applications. Albeit low-power features and high parallelism of ACIM, the non-ideality arising from process variation hampers classification accuracy. To address this issue, conventional circuit-level methods augment more circuit resources, which sacrifices energy and area efficiency. Alternatively, various non-ideality-aware frameworks have been proposed to leverage the redundancies and error tolerance inherent in DNN-based designs in recent years; i.e., mitigating the impact of non-ideality at both algorithm and architecture levels. The algorithmic innovations improve the accuracy while maintaining its computational efficiency. Moreover, at the architecture level, a sequential but error-free near-memory-computing (NMC) mode has been introduced in ACIM for flexible adjustment of computing reliability based on different application scenarios. This paper presents the design challenges and foundational concepts of various non-ideality-aware frameworks in a comprehensive way. Besides, the representative related works are reviewed and summarized. Finally, we conclude the paper and point out future works.