Effective Analytical Placement for Advanced Face-to-Face-Bonded Circuit Designs

3D chip integration technology, which consists of bonding terminals as die-to-die vertical connections, has attracted a lot of attention due to its many benefits over monolithic integration technology. Compared to previous through-silicon vias (TSVs) interconnects, the recent advancement in face-to-face (F2F) bonding 3D ICs technology can provide better fine-grained and silicon-space overhead-free 3D interconnections. The F2F bonded structure brings a new sweet spot for 3D integration technology while bringing critical challenges for placement algorithm design at the same time. In this paper, we present an effective algorithm to address this F2F-bonded 3D placement problem in several stages. First, a hypergraph partitioning technique using a multilevel framework is used to obtain an appropriate partitioning result under architecture constraints quickly. Then a multi-layer objective function based on an electrostatics model is used to co-optimize the objective over multiple layers. Finally, abacus-based legalization and detailed placement with cell-matching techniques are adopted to optimize the results further. Compared with the winner of the ICCAD 2022 CAD Contest, experimental results show that our algorithm can achieve comparable final total wirelength and 3.41× speedup.