Pseudo differential DQS receiver for eliminating channel Hi-z noise

This paper presents a pseudo differential DQS receiver to eliminate the unexpected glitch coming from channel hi-z noise for DDR SRAM. This unexpected glitch is happened in both DQS and DQSB are VDDQ termination status. This Hi-z status DQS/DQSB have logically ‘High’ but since DRAM receiver amplify this two differential signal’s level difference with high sensitivity so receiver’s output can be fluctuated by Hi-z noise. This glitch leads abnormal DRAM WR DQ domain change function error. To mitigate this glitch, several schemes proposed but those scheme used one direction’s offset so it just can support certain system which already known the amount of offset and it is suffered by the duty distortion due to that offset. Proposed the advanced DQS receiver architecture has wide immunity range of Hi-z noise regardless with offset direction and prevents duty distortion by adopting the internal common mode compensation scheme. Experimental results show over ±100mV voltage offset tolerance and achieve over 4800Mpbs data rate without output duty distortion.