TCAD Study on Strain Engineering in Vertical Channel Gate-all-around Transistor

In this paper, a TCAD simulation study of strain engineering in vertical channel gate-all-around (VCG) devices is presented. A replacement-metal-gate (RMG) process is proposed to fabricate the devices on the conventional CMOS platform. With the careful calibration of initial stress distribution in molecular beam epitaxy grown supper lattice by Raman spectrum, the stress evolution model of VCG devices is established. TCAD simulation results show that the asymmetric and bottom-up device and process paradigms strongly affect the stress redistribution and evolution during process fabrication as well the stressor configuration. It’s found that the formation of vertical channel, source/drain epitaxy and RMG strongly affects the stress redistribution. With the same stressor configuration as lateral GAA devices, the channel stress direction is totally opposite, i.e. compressive stress for Si S/D/SiGe channel/Si S/D structure and tensile stress for SiGe S/D/Si channel/SiGe S/D. With the simulation of electrical characteristics, a preliminary optimized VCG device structure for CMOS application is designed to be SiGe S/D/Si channel/SiGe S/D with 10 nm × 20 nm cross section.