An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process

In order to address the radiation-induced effects in the timing units of configurable logic block(CLB), a design scheme for an anti-single event flip-flop based on master-slave D flip-flops has been proposed. This design scheme first optimizes the radiation-hardened structure of the dual-delay chains in SETTOFF and combines it with the functionality of the CLB timing unit to design a flip detection D flip-flop circuit. Then, the full-custom design method is used to complete the schematic and layout design of the circuit. Finally, the designed circuit was simulated using the TSMC 28nm CMOS process parameters in SPECTRE. The simulation results showed that the circuit has correct logical functionality and good transient characteristics. The experimental results demonstrated that the proposed D flip-flop can achieve the basic function of the CLB timing unit. The layout area is approximately 3.36μm
²
, and the power-delay product is about 1.01fJ. The simulation results revealed that the output Q exhibited a glitch with a voltage of approximately 0.3V, which was successfully corrected to the correct logic value.