A Cost-efficient Hybrid Gate Driver For SiC MOSFETs and IGBTs

A gate driver with hybrid pull-up structure is proposed, which is suitable for driving both SiC MOSFETs and IGBTs. Instead of using additional external components with conventional charge pump and bootstrap structures, a self-biased floating driving technique is presented, which can effectively reduce cost and chip area. The hybrid pull-up structure consists of both NMOS and PMOS transistors, where the NMOS is used to accelerate the transient speed during turn-on duration while rail-to-rail output guaranteed by the PMOS. The proposed circuit is validated in an 0.18 μm BCD technology. The results demonstrate that a maximum source current of 11.9 A is realized with a 24.4 ns rise time driving a 10nF load capacitor.