A High Speed, Low Power and Low Phase Noise Divider for Wideband Application

A low phase noise frequency divider is applied accompany with 2 stages of buffer for wideband application in this paper. With cross coupled inverter in it, this divider could generate quadrature phases and criticize the phase mismatch coming from input signal. Implemented in 28nm CMOS, the clock chain has locking range from 400MHz to 20GHz, and criticizes the phase error from 10° to 1.4°.