A Novel 16-bit ADC Based on Third-order Σ-∆ Modulator with Zero Optimization

In this paper, a Sigma Delta modulator with a third-order feed-forward structure incorporating zero optimization is proposed, which utilizes chopper to reduce the perturbation of the first-stage integrator caused by flicker noise and misalignment. The digital extraction filter adopts a three-stage cascade structure of CIC filter, compensation filter and half-band filter, in which the extraction rate can realize the output data at different rates from 312.5Hz to 20kHz. The final simulation results show that the overall signal-to-noise ratio of the Sigma Delta modulator after adding the zero optimization is 112.6dB, and the effective number of bits is 18.41-bit, which meets the 16-bit accuracy requirement of the system and is suitable for analog circuit implementation.